Memory devices with charge-trapping layers, especially SONOS memory cells comprising oxide-nitride-oxide layer sequences as storage medium, are usually programmed by channel hot electron injection. U.S. Pat. No. 5,768,192 and U.S. Pat. No. 6,011,725, which are both incorporated herein by reference, disclose charge-trapping memory cells of a special type of so-called NROM cells, which can be used to store bits of information both at the source and at the drain below the respective gate edges. The programmed cell is read in reverse mode to achieve a sufficient two-bit separation. Erasure is performed by hot-hole injection. The current consumption of each cell during programming with fully driven transistor is about 100 μA. An increment of charges towards the middle channel region significantly reduces the number of possible programming cycles. Therefore, it is not possible to shrink the cell to the sub-100-nm technology since the increasing amount of charges in the middle channel region cannot be completely neutralized during the reprogramming process. Thus, the performance of the memory cell will deteriorate with an increasing number of programming cycles.
U.S. Patent Application Publication No. 2003/0185055 A1 and a corresponding paper of C. C. Yeh et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory”, 2002 IEEE, both of which are incorporated herein by reference, disclose a non-volatile semiconductor memory cell with electron-trapping erase state, which is operated as flash memory and is able to store two bits. The erasure takes place by Fowler-Nordheim tunneling of electrons from either channel or gate electrode into the storage layer of a conventional charge-trapping layer sequence, for example an ONO layer sequence. In programming this memory, electric holes are injected into the non-conducting charge-trapping layer. Hot hole injection can be induced at source and drain, which means, at both ends of the channel. This operating method avoids high programming currents.
In a virtual-ground array of memory cells that are addressed by wordlines and bitlines, the programming of an individual cell by hot-hole injection is performed by the application of a lower and a higher programming voltage to the two bitlines that are connected to the source/drain regions of the memory cell that is to be programmed. The location of the programmed bit at either end of the channel region in the vicinity of one of the source/drain regions is selected by the direction of the applied source/drain voltage. A negative voltage, typically about −7 V, is applied to the gate electrode of the cell transistor to be programmed. As the wordlines connect all the gate electrodes along a row of memory cells, this negative voltage is also present at the gate electrodes of the neighboring cell transistors of the same row in which the cell transistor that is to be programmed is situated. All the other gate electrodes within the array are on 0 V (“ground”). The programming voltages are typically, for example, 0 V and +4 V.
By the application of this potential difference at the source/drain regions of the memory cell to be programmed, an injection of hot holes is generated at drain, which is connected to the high programming voltage of 4 V. If the source/drain region at the other end of the adjacent memory cell in the same row of memory cells is on 0 V, the source/drain voltage of the adjacent memory cell transistor is also sufficient for a programming of this transistor, which is not desired. Therefore, a so-called inhibit voltage is applied to this neighboring source/drain region, which may be typically, for example, +2 V, in order to reduce the source/drain voltage of that transistor to a value that is sufficiently low to guarantee that no programming occurs in the neighboring memory cell. This is possible because the programming requires a minimal value of the source/drain voltage, on which the efficiency of the injection mechanism strongly depends. All the other bitlines can be on 0 V so that the source/drain voltages of all the memory transistors that are not to be programmed are typically 0 V or 2 V, and these memory cells are not programmed. The programming procedure starts with the application of the inhibit voltage to the neighboring bitline, and then the programming voltage is applied to the bitlines that are connected to the memory cell that is to be programmed. The exact value of the voltages of the other bitlines is not important for the programming process so that the voltages of those bitlines may vary within certain limits. However, it is necessary that the programming voltage is applied to only one of the memory cells of the row of memory cells that are addressed by the same wordline.
Memory products with a virtual-ground architecture usually comprise master bitlines that are connected to groups of bitlines via especially arranged select transistors. The bitlines that succeed each other along the rows are alternatingly connected to different master bitlines so that the different programming voltages can be applied to adjacent bitlines via the selection transistors. In a typical arrangement of the array, the groups of bitlines that are connected to the same master bitline comprise, for example, four or eight bitlines each. A multiplexer circuit is arranged to switch the select transistors so that no more than one bitline can be connected simultaneously to one of the master bitlines. The sequential application of the inhibit voltage the programming voltages to different bitlines requires a significantly more complicated switching circuitry. This is a drawback of this memory architecture comprising charge-trapping memory cells that are programmed by hot-hole injection.